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M68Z128W
3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
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LOW VOLTAGE: 3.0V (+0.6V / -0.3V) 128Kb x 8 LOW POWER SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW VCC DATA RETENTION: 1.4V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER INTENDED for USE with ST ZEROPOWER(R) and TIMEKEEPER(R) CONTROLLERS
TSOP32 (N) 8 x 20mm
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DESCRIPTION The M68Z128W is a 1 Mbit (1,048,576 bit) Fast CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 3.0V (+0.6V / -0.3V) supply, and all inputs and outputs are TTL compatible. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z128W is available in the standard 450mil-wide TSOP type 1 package.
Figure 1. Logic Diagram
VCC
17 A0-A16
8 DQ0-DQ7
Table 1. Signal Names
A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS NC Address Inputs Data Input/Output Chip Enable 1 Chip Enable 2 Output Enable Write Enable
W E1 E2 G M68Z128W
VSS
Supply Voltage Ground Not Connected Internally
AI01878B
March 2000
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M68Z128W
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG VIO (2) VCC IO (3) PD Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltage Supply Voltage Output Current Power Dissipation Value 0 to 70 -65 to 150 -0.5 to VCC + 0.5 -0.5 to 4.6 20 1 Unit C C V V mA W
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Up to a maximum operating VCC of 3.6V only. 3. One output at a time, not to exceed 1 second duration.
Figure 2. TSOP Connections
A11 A9 A8 A13 W E2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1
32
8 9
M68Z128W
25 24
16
17
AI00698B
G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
the 1,048,576 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low, E1 is Low and E2 is High. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, t E2HQX and t GLQX, but data lines will always be valid at tAVQV. WRITE MODE The M68Z128W is in the Write mode whenever the W and E1 pins are Low, with E2 High. Either the Chip Enable inputs (E1 and E2) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. Write begins with the concurrence of both Chip Enables being active with W low. Therefore, address setup time is referenced to Write Enable and both Chip Enables as tAVWL , tAVE1L and t AVE2H respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E1, W, or the falling edge of E2. If the Output is enabled (E1 = Low, E2 = High and G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVE1H before the rising edge of E1 or for tDVE2L before the falling edge of E2, whichever occurs first, and remain valid for tWHDX, tE1HDX or tE2LDX.
READ MODE The M68Z128W is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and both Chip Enables (E1 and E2) are asserted. This provides access to data from eight of
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Table 3. Operating Modes
Operation Read Read Write Deselect Deselect
Note: 1. X = VIH or VIL.
E1 VIL VIL VIL VIH X
E2 VIH VIH VIH X VIL
W VIH VIH VIL X X
G VIH VIL X X X
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z Hi-Z
Power Active Active Active Standby Standby
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 15ns 0 to 3V 1.5V
Figure 3. AC Testing Load Circuit
3.3V
Note: Output Hi-Z is defined as the point where data is no longer driven.
1213 DEVICE UNDER TEST 1378
OPERATIONAL MODE The M68Z128W has a Chip Enable power down feature which invokes an automatic standby mode whenever either Chip Enable is de-asserted (E1 = High or E2 = Low). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E1, and E2 as summarized in the Operating Modes table.
OUT
CL = 50pF or 5pF
CL includes JIG capacitance
AI00697
Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol CIN COUT (2) Parameter Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 8 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. Outputs deselected.
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M68Z128W
Figure 4. Block Diagram
A (9) A CHIP ENABLE. DQ (8) DQ INPUT DATA CTRL I/O CIRCUITS COLUMN DECODER ROW DECODER MEMORY ARRAY
VCC VSS
CHIP ENABLE. CHIP ENABLE (8) A A
W E1 E2 G
AI00665
Table 6. DC Characteristics (TA = 0 to 70C; VCC = 3.0V + 0.6V / -0.3V)
Symbol ILI ILO ICC1
(1)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VOUT VCC VCC = 3.6V, (-70) VCC = 3.6V, E1 = VIH or E2 = VIL, f =0 VCC = 3.6V, E1 VCC - 0.2V or E2 0.2V, f =0
Min
Typ
Max 1 1
Unit A A mA A A V V V V
20 15 0.4 -0.5 2
40 300 15 0.8 VCC + 0.5 0.4
ICC2 (2) ICC3 (3) VIL VIH VOL VOH
IOL = 2.1mA IOH = -1mA 2.4
Note: 1. Average AC current, Outputs open, cycling at tAVAV minimum. 2. All other Inputs at V IL 0.8V or VIH 2.0V. 3. All other Inputs at V IL 0.2V or VIH VCC -0.2V.
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Table 7. Read and Standby Modes AC Characteristics (TA = 0 to 70C; VCC = 3.0V + 0.6V / -0.3V)
M68Z128W Symbol Parameter Min tAVAV tAVQV (1) tE1LQV (1) tE2HQV (1) tGLQV (1) tE1LQX (3) tE2HQX (3) tGLQX (3) tE1HQZ (2,3) tE2LQZ (2,3) tGHQZ (2,3) tAXQX (1) tPU tPD Read Cycle Time Address Valid to Output Valid Chip Enable 1 Low to Output Valid Chip Enable 2 High to Output Valid Output Enable Low to Output Valid Chip Enable 1 Low to Output Transition Chip Enable 2 High to Output Transition Output Enable Low to Output Transition Chip Enable 1 High to Output Hi-Z Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Chip Enable 1 Low or Chip Enable 2 High to Power Up Chip Enable 1 High or Chip Enable 2 Low to Power Down 10 10 10 0 0 0 10 0 70 25 25 25 70 70 70 70 35 -70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 50pF (see Figure 3). 2. CL = 5pF (see Figure 3). 3. At any given temperature and voltage condition, tEIHQZ + tEZHQZ is less than tEILQX and tEZLQX, tGHQZ is less than tGLQX for any given device.
Figure 5. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI01078
Note: E1 = Low, E2 = High, G = Low, W = High.
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Figure 6. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV A0-A16 tAVQV tE1LQV E1 tE1LQX tE2HQV E2 tE2HQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00805
VALID tAXQX tE1HQZ
tE2LQZ
tGHQZ
Note: Write Enable (W) = High.
Figure 7. Standby Mode AC Waveforms
E1
E2 ICC1 ICC2 tPU 50% tPD
AI00806B
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Table 8. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 3.0V + 0.6V / -0.3V)
M68Z128W Symbol Parameter Min tAVAV tAVWL tAVWH tAVE1H tAVE2L tWLWH tWHAX tWHDX tWHQX (2) tWLQZ (1,2) tAVE1L tAVE2H tE1LE1H tE2HE2L tE1HAX tE2LAX tDVWH tDVE1H tDVE2L Write Cycle Time Address Valid to Write Enable Low Address Valid to Write Enable High Address Valid to Chip Enable 1 High Address Valid to Chip Enable 2 Low Write Enable Pulse Width Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Output Hi-Z Address Valid to Chip Enable 1 Low Address Valid to Chip Enable 2 High Chip Enable 1 Low to Chip Enable 1 High Chip Enable 2 High to Chip Enable 2 Low Chip Enable 1 High to Address Transition Chip Enable 2 Low to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable 1 High Input Valid to Chip Enable 2 Low 0 0 60 60 0 0 30 30 30 70 0 60 60 60 55 0 0 0 25 -70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 5pF. 2. At any given temperature and voltage condition, tWHQX is less than tWLQZ for any given device.
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M68Z128W
Figure 8. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00807
tWHAX
tWHQX
Note: Output Enable (G) = Low.
Figure 9. Chip Enable Controlled, Write AC Waveforms (1,2)
tAVAV A0-A16 VALID tAVE1H tAVE1L E1 tE1LE1H tE1HAX
tAVE2L tAVE2H E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L
Note: 1. Output Enable (G) = High. 2. If E1 goes High or E2 goes Low simultaneously with W high, the output remains in a high-impedance state.
tE2HE2L
tE2LAX
AI00808
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M68Z128W
Table 9. Low V CC Data Retention Characteristics (TA = 0 to 70C)
Symbol ICCDR (1) VDR (1) tCDR
(1,2)
Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time
Test Condition VCC = 3V, E1 VCC - 0.2V, E2 0.2V, f = 0 E1 VCC - 0.2V, E2 0.2V, f = 0 E1 VCC - 0.2V, E2 0.2V, f = 0
Min
Typ 0.01
Max 2
Unit A V ns ns
1.4 0 tAVAV
tR (2)
Note: 1. All other Inputs at V IH VCC - 0.2V or VIL 0.2V. 2. See Figure 10 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time.
Figure 10. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 3V VDR > 1.4V tCDR E1 VDR - 0.2V E1 2.2V tR
E2 0.2V E2 0.8V
AI00664
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Table 10. Ordering Information Scheme
Example: Device Type M68Z Device Function 128 = 1 Mbit (128Kb x8) Operating Voltage W = 3V +0.6/-0.3V Speed -70 = 70 ns Package N = TSOP32 type 1 (8 x 20mm) Temperature Range 1 = 0 to 70 C Shipping Method T = Tape & Reel Packing M68Z128W -70 N 1 T
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
Table 11. Revision History
Date November 1999 03/20/00 First Issue TSOP32 Package Mechanical Data changed (Table 12) Revision Details
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M68Z128W
Table 12. TSOP32 (Type I) - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D D1 e E L CP N 32 0.500 0.050 0.950 0.150 0.100 19.800 18.300 - 7.900 0.500 0 Min Max 1.200 0.150 1.050 0.270 0.210 20.200 18.500 - 8.100 0.700 5 0.100 32 0.0197 0.0020 0.0374 0.0059 0.0039 0.7795 0.7205 - 0.3110 0.0197 0 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 - 0.3189 0.0276 5 0.0039 inch
Figure 11. TSOP32 (Type I) - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale.
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M68Z128W
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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